1. Field of the Invention
The present invention relates to a random number generation circuit which generates random numbers.
2. Related Art
A random number generation circuit provided with an oscillation circuit connected to one or three CMOS inverters, a flip-flop which latches an oscillation signal generated by this oscillation circuit and a feedback shift register which generates pseudo-random numbers based on an output signal of the flip-flop is known (see Japanese Patent Laid-Open No. 2002-236582).
This type of conventional random number generation circuit inputs the output signal of the flip-flop as a seed to the feedback shift register. It is possible to improve randomness of random numbers using a feedback shift register or the like at subsequent stage to a certain degree. However, it is not possible to reduce the probability of collision of finally obtained random numbers unless the seed to be input to the feedback shift register has a sufficient level of randomness.
The probability of collision of random numbers depends on the uncertainty of the seed generated by the flip-flop and this uncertainty mainly depends on the fact that the oscillation circuit composed of the CMOS inverters is unstable with respect to fluctuation of temperature and supply voltage. With this uncertainty alone, according to the conventional method, there is a high probability that the same seed may be generated within a random numbers generating period, as long as there are not considerable disturbance factors in the temperature and supply voltage or the like. Therefore, it is difficult for the conventional method to reduce the probability of collision of random numbers. In this way, the conventional random number generation circuit has a problem that it is not possible to obtain high quality random numbers.